Assembly Using X-WireTM Insulated Bonding Wire Technology

As the semiconductor industry continues to move towards higher pin count, finer pitch, multi-row and multistack devices, wire bonding becomes an increasing challenge for today’s advanced packaging processes. Insulated bonding wire technology, known as X-WireTM, has been identified on the 2006 ITRS Roadmap for Semiconductors [1], as a viable, cost-effective solution to enable complex package designs, enhance package performance, and improve the yield of high-density packaging. In order to successfully implement insulated wire bonding, low cost integration into the existing packaging assembly infrastructure is of utmost importance. In particular, it is a requirement that the insulated bonding wires demonstrate wirebonding and package assembly performance which meets industry standard wire bond package test specifications when used on existing wirebonding and packaging assembly platforms. This paper will discuss various methods, techniques and processes developed to date that allow insulated wire packages to be assembled with high yield and reliability using current production equipment. Proper capillary selection and wire bonder setup, as well as correct use of bond parameters, loop parameters, plasma parameters and other advanced wirebond and packaging techniques will be highlighted. Background System Packaging Selection IC packaging is often described as the linkage between the silicon and the system. In layman’s terms, electronics packaging can be described as the process of connecting chips together to create an electronic system. The ultimate technical goal is to deliver the highest performance chip function to the end-user at the lowest cost; however, limitations in packaging and chip manufacturing technology create a ‘drag’ in the system which reduce the final performance to the user. These limitations are the compromises that chip designers and systems architects have had to make to accommodate the shortcomings in the interconnection (packaging) technology available. Chip Level Interconnection An important first step in electronics packaging interconnections are the chip-level, (also called first-level) interconnects. This interconnect will dictate to a high degree how much performance can be achieved from a chip. Performance is critical; however, an IC product manager cannot consider performance in isolation to other economic factors. Important considerations in a full benefit/cost tradeoff analysis can be grouped into the following categories: (1) Cost, (2) Performance, (3) Size/Density, and (4) Time-to-Market. Packaging technologies are typically evaluated on this basis. Although many types of first-level interconnection technologies exist to connect chip-to-chip, and chip-tosubstrate, two primary methods continue to dominate the industry: (1) Wire bonding & (2) Flip Chip (a form of Wafer Level Packaging), with wirebonding holding greater than 90 percent of the market. Over time, niche technologies such TAB (tape-automated-bonding) and more recently, throughsilicon-via (TSV), have emerged to provide alternate solutions to specific interconnection challenges. Insulated Wire Bonding The semiconductor industry has been seeking a viable insulated wire bonding solution for almost as long as wirebonding technology has been available [2,3]. The benefits of insulated wire bonding have been well known and clear for many years: With respect to a full benefit/cost tradeoff analysis, insulated bonding wire provides: 1) Cost: a. The ability to use the lowest cost manufacturing infrastructure, which is wirebonding. 2) Performance: a. The ability to allow more interconnections per unit area at the chip level, enabling low cost ‘die shrink’ chips and reducing padlimitations. b. The ability to connect chips directly together for highest bandwidth connection, eliminating layers of chip, substrate and board level wiring and allowing flexible routing. c. The ability to bring signal and ground wires very close together to minimize inductance. 3) Size: a. The ability to place chips tightly together, known as ‘brick-walling’, not requiring a wirebond fan-out or keep-out area. b. The ability to connect stack dies directly and flexibly in a wide variety of configurations. 4) Time-to Market: a. The ability to use existing chips immediately without additional chip or wafer processing. b. The flexibility to applied on a wide range of applications Because of its flexibility and cost effectiveness and because it leverages a significant amount of proven human capital,